An improved method to extract the capacitances of an integrated circuit

W. van Til
Delft University of Technology
Department Materials Science and Technology
Rotterdamseweg 137
2628 AL Delft

Before the fabrication of a chip (an integrated circuit), the correctness of its layout should he verified. The verification step ensures that no chip with an incorrect layout is taken into production. This verification could be done by simulating the equivalent circuit or by static analyses. Due to the advancements of the integrated circuit technologies, the verification step becomes more and more important. Because of developments like the decrease in size of the features on the integrated circuits and reduction of the switching times, the electrical behavior of an integrated circuit is determined more and more by parasitic elements, like resistances, inductances, and capacitances. Hence, to determine the behavior of an integrated circuit, the parasitic elements must be known.

There are several methods to determine the capacitances. One of these methods is the Boundary Element Method. In the Boundary Element Method the surfaces of the conductors are divided into a total of N panels. For each panel the capacitances are determined and placed into an N x N matrix. The main problem of this method is the necessary inversion of a dense matrix. The inversion of a dense N x N matrix requires O(N*N*N) operations, where N is the number of elements. Since the number of elements increase, the size of the matrix increases and the computation time (the number of operations) increases. For a large number of elements the inversion becomes unmanageable. To reduce the computation time, the capacitances can be approximated. The methods to approximate the capacitances must be efficient and accurate. An algorithm is efficient if the computation time and the necessary amount of memory are as low as possible. Two existing algorithms that more or less satisfy the above are the Hierarchical Schur algorithm and FastCap algorithm. In my assignment I have developed a combination of these former two algorithms, that requires less time and memory than both of them. The improved algorithm partitions the layout of an integrated circuit into non-overlapping windows, which are combined into overlapping blocks. The capacitances, extracted for each block, are combined to the capacitances for the entire integrated circuit.

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Laatst aangepast op 06-02-2002 door Kees Vuik